FIG. 1 schematically shows the general organization of an interline area image sensor having an array of photodiode sensor elements. Several of the sensor elements 16 which are shown in FIG. 1 are identified as A, B, C, D, E, F, G, H and I. The elements are arranged in columns and rows. Photo charge is integrated in each photodiode and, at a predetermined time, appropriate bias voltage pulse signals are applied to the transfer gate electrodes causing the charge to transfer from the photodiode to a vertical CCD shift register 26. Those skilled in the art will appreciate that the shift registers 26 conveniently can be constructed in two phase buried channel architecture.
Each CCD shift register 26 will be under the control of a plurality of electrodes 26a and 26b (see FIG. 3). When a potential is applied to an electrode, a depletion region is formed under that electrode. Consider, for example, a buried channel CCD shift register which is formed with a p-substrate covered with a silicon dioxide layer with an n-buried channel on which there has been deposited a row of closely spaced electrodes for operating a shift register 26. FIG. 3 illustrates a single pixel of a conventional interline transfer CCD image sensor. The electrodes 6a and 26b may be one half stage of either a four phase or a pseudo two phase shift register as would be appropriate for an interlaced image sensor. In the pseudo two phase implementation electrodes 26a and 26b are driven from the same bias source with electrodes 26a and 26b being the transfer and storage regions, respectively. If the two electrodes 26a and 26b each contain both a transfer and storage region, then they provide one complete CCD stage of what we will call a true two phase CCD. Such a two phase CCD is effective in a non-interlaced interline CCD image sensor.
After the signal charge is transferred from the photodiode, 16, to the vertical shift register, 26, the signal charge may be shifted vertically down the shift registers, 26, a line at a time, into a horizontal shift register, 27 (see FIG. 1). The pixel charge information is shifted to a buffer amplifier where it is converted to an output voltage proportional to the pixel charge, and becomes available for off-chip signal processing, storage and/or display.
Both image lag and blooming severely degrade the performance of interline transfer type image sensors. Both of these phenomena must be controlled at the sensor design stage. Image lag is the persistence of an image into subsequent fields and is a direct consequence of a photodiode that cannot be reset to a fully depleted condition upon readout of the signal from the photodiode to the vertical CCD shift register. The effect of this is to leave a residual signal behind that becomes signal in subsequent fields. The inability to fully reset the photodiode is caused by the doping distributions required to achieve another desirable feature in the sensor, namely antiblooming via a vertical antiblooming drain. Blooming results when an area of the image sensor receives an amount of illumination that generates signal charges in excess of the charge capacity of either the photodiode or a stage of the vertical shift register. The excess charge spreads or "blooms" along the vertical shift register, thus contaminating the signal from other pixels. Blooming control is essential in applications wherein the light level is not controlled. A vertical overflow drain (VOD) is a commonly used technique for controlling antiblooming. There is a need in the art for an interline transfer CCD fabrication design that permits a fully depletable photodiode for complete elimination of image lag while simultaneously retaining the vertical overflow drain for antiblooming protection.
As shown in FIG. 2a, an example of a prior art interline CCD image sensor 10 with vertical overflow antiblooming protection is shown in cross-section. A p-well 12 is ion implanted into an n-type substrate 14. An n-layer 16a is added in the well 12. A p-layer, 16b, on the n-layer 16a completes the photodiode 16. The p-layer, 16b, is added to attempt to fabricate a fully depletable photodiode. A gate oxide 18 is formed on the substrate surface. Appropriate channel stops 17 and 17a include a thick oxide with a p-type diffusion beneath are also provided. An n-buried channel 20 is formed in the p-well 12 and spaced from the photodiode 16 (FIG. 1). A polysilicon or other metallic gate 22 is positioned on the gate oxide 18 and is both one of the CCD phase gates as well as the transfer gate from the photodiode to the buried channel CCD. First, the p-well ion implant doping is placed everywhere except that it is omitted from under the photodiode. Thereafter a high temperature and/or long time furnace diffusion step occurs that drives the p-well both vertically and horizontally until it is driven completely beneath the center of the photodiode. The overflow current to the substrate occurs at the point shown in FIG. 2a where the p-well doping is a minimum. This process does not permit a fully depletable diode because of the potential barrier shown by the arrows in FIG. 2b. In FIG. 2b, the electrostatic potential for both readout of the CCD and reset of the photodiode is shown. In the first situation (readout of the vertical CCD), no or only small positive potential is applied to the transfer gate 22. In the second situation, a more positive potential is applied to the gate 22 and charge flows from the photodiode to the buried channel. However, a large electrostatic potential barrier still occurs between the center of the photodiode and the edge of the transfer gate. This is a direct result of the p-well 12 doping gradient that arises from the diffusion of the p-well under the photodiode. The potential barrier prevents the complete depletion of the photodiode 16 through the transfer gate, and thus also inhibits the elimination of image lag.
The object of this invention is to provide an interline CCD which includes effective vertical overflow drain blooming control and eliminates image lag.